Ritwik Basyas Goswami supervised by Dr. Zia AbbasΒ received his Master of ScienceΒ in Electronics and Communication Engineering (ECE). Hereβs a summary of his research work on ML-Accelerated Optimization Strategies for CMOS & FinFET Circuits:
The rapid evolution of semiconductor technologies, marked by the transition to FinFETs and increasingly complex CMOS nodes, has intensified challenges in circuit design. Process variations, aging effects, and stringent performance requirements demand innovative strategies to balance precision, reliability, and computational efficiency. This thesis explores machine learning (ML)-driven method- ologies to address these challenges, focusing on scalable optimization frameworks for next-generation integrated circuits.
Central to this work is the development of advanced machine learning (ML) models suited for circuit data modeling. A chained architecture is introduced to capture process-induced variations in leakage power, voltage, and current across diverse technology nodes and operating conditions. By integrating temperature and voltage fluctuations into its design, this framework significantly enhances prediction ac- curacy, enabling robust modeling of nanoscale devices across tech-nodes. Complementing this, a novel automated system leverages ML to streamline analog circuit optimization, reducing manual iterations and simulation overhead while maintaining compliance with designer specifications.
The thesis further proposes optimization strategies accelerated by ML to address transistor sizing and aging mitigation. A multi-objective evolutionary algorithm framework is designed to rapidly optimize digital logic cells, achieving substantial improvements in power-delay metrics without reliance on traditional simulator-heavy workflows. For FinFET-based systems, an aging-aware optimization methodology dynamically adjusts device parameters to counteract reliability degradation from NBTI and HCI effects, ensuring sustained performance across operational lifetimes. These approaches collectively bridge the gap between computational efficiency and design robustness.
By unifying ML-driven modeling with intelligent optimization, this research advances the integration of automation in electronic design. The proposed frameworks not only enhance circuit reliability and efficiency but also empower designers to navigate the complexities of advanced CMOS and FinFET technologies. These contributions lay a foundation for adaptive, high-performance systems in applications ranging from IoT devices to industrial electronics, underscoring the transformative potential of machine-learning (ML) in modern VLSI design.
July 2025