Mohammad Rehan Akhtar was recognized with the Ritesh Tiwari Outstanding Masters Thesis Award 2026 for his research on Integrated Standard Cell Characterization and Complex Circuit Analysis in CMOS/FinFET Digital Circuit Design under the guidance of Dr. Zia Abbas.

In his thesis, Rehan addresses the challenge of reliability-aware modeling and optimization in nanoscale digital ICs, particularly in advanced CMOS and FinFET technology nodes. As technology scales below 16 nm, digital circuits experience severe process variations, increased leakage power, and aging-induced deterioration mechanisms like Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), which significantly impact delay, power consumption, and long-term circuit reliability. When exploring large design spaces, the Conventional Electronic Design Automation (EDA) methodologies rely on exhaustive SPICE simulations and worst-case corner analysis, which are computationally expensive and often overly pessimistic.

The novelty of the thesis lies in integrating three traditionally separate domains of integrated circuit design: device-level physics, machine learning-based modeling and circuit-level characterization. Overall, the thesis provides a systematic treatment of the problem of reliability-aware circuit modeling and optimization.

The thesis addresses the above-mentioned challenge across multiple levels of abstraction, having a reasonable theoretical depth along with practical applicability.

• At the device and standard cell level, the work proposes the RelOps framework to mitigate aging effects through machine learning-guided transistor sizing optimization in FinFET circuits. 
• At the modeling level, the thesis introduces PIDArc, a novel physics-informed machine learning architecture designed to capture complex leakage power behavior under aging and variation conditions. 
• At the circuit level, the OptiMo framework extends the analysis to complex digital circuits by enabling automated estimation and optimization of delay and leakage power. 

To conclude, the thesis provides a comprehensive design pipeline from device-level reliability modeling to circuit-level performance analysis, making it a well-rounded contribution to the field.