Prof. Zia Abbas K Agarwal and his students A Jain and Deepthi Amuru presented a paper on Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits at the IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan from 18 – 21 April. Research work as explained by the authors:
This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. Therefore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate High-K digital cells show a reduction in delay and leakage up to 36.7% and 18.8%, respectively improving computational efficiency by several orders.
The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA symposium), first held in 1983, held once every two years, gathers experts from all over the world and has always been fruitful and productive. Every year, scientists and engineers discuss and present the state-of-the-art technology R&D and macro development of the industry’s future. It is considered the most important event in Taiwan’s semiconductor industry and highly anticipated by local companies. Taking advantage of the information learned during the conference, the symposium hopes to create new opportunities for Taiwan’s semiconductor industry. The VLSI-TSA symposium is becoming more significant since Taiwan not only occupies a prominent position in the global semiconductor industry, but also is increasingly competitive globally in IC design technology and communications information products.