[month] [year]

VDAT-2024

Venkata Apparao Yempada, part-time Ph.D student working with Dr. Srivatsava Jandhyala presented a paper on Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs at the VLSI Design and Test (VDAT-2024) conference held at Vellore Institute of Technology, Vellore from 1 to 3 September.

Here is the summary of the research work as explained by the authors:  Integration challenges of perovskites-based ferroelectrics increased the focus on usage of non-perovskites for the design of Negative Capacitance (NC) FETs. To meet the sub60mV/decade subthreshold swing without compromising the on-state performance in advanced nodes, integration of Ferroelectric layer in the gate stack of a lateral Heterojunction Tunnel FET(HTFET) is an optimum choice. Ferroelectric materials, when stabilized, exhibit hysteresis-free negative capacitance characteristics that improve the subthreshold swing and thereby the on-state performance TFET. In this work we explored the CMOS compatible non-perovskites-based ferroelectrics, such as doped Hafnium oxide (HfO2), and Hafnium Zirconium oxide (HZO2), for designing Staggered gap Heterojunction Ferroelectric TFETs(He-FeTFET), for low power logic applications. Using SILVACO TCAD, a commercial Technology CAD software, an exhaustive simulation study is made tuning the device parameters, to achieve a hysteresis-free steeper switching with sub-60 mV/decade subthreshold swing without compromising the on-state performance and to achieve very low leakage, of the order of sub-fA. The material system, dopings of the device and the thickness of the ferroelectric layer, necessary to achieve a point subthreshold-swing of lesser than 10 mV/decade and large on-to-off current ratio (Ion/Ioff ) ≈ 1010 for the He-FeTFET are presented and performance is compared with a plain HTFET. 

September 2024