Siddhant Garg supervised by Dr. Suresh Purini received his Master of Science – Dual Degree in Electronics and Communication Engineering (ECD). Here’s a summary of his research work on ArchXBench and ArchXAgent: A Benchmark Suite and Agentic Workflow for LLM-Driven RTL Synthesis

Modern System-on-Chip (SoC) datapaths rely on complex arithmetic, cryptographic, signal-processing, and machine-learning accelerators. RTL development for these systems, though, is still mostly manual and iterative. Large language models (LLMs) have shown real promise in code generation, yet existing HDL benchmarks focus on simpler circuits and do not adequately cover hierarchical composition, deep pipelining, or architecture-level constraints. This thesis makes two contributions. The first is ArchXBench, a benchmark suite for LLM-driven RTL synthesis with tasks organized from Level-0 through Level-6 (including Level-1 sublevels) and artifacts that include problem descriptions, design specifications, and testbenches. The second is ArchXAgent, an agentic workflow built on a dual-agent architecture: a Green evaluation agent and a Purple generation agent. It supports iterative generate, evaluate, and refine loops, offers structured feedback and synthesisaware evaluation, and is compatible with the A2A protocol for reproducible external assessment. Beyond describing these systems, the thesis records concrete benchmark contributions to ArchXBench, covering artifacts authored and refined (problem descriptions, design specifications, and testbenches across multiple levels). It also integrates ArchXAgent implementation details drawn from repository code and documentation. All quantitative claims are limited to values validated against project artifacts and the ArchXBench paper baseline.

July 2026