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Shashwat Shrivastava – Dual Degree ECE

Shashwat Shrivastava received his MS  Dual Degree in Electronics and Communication Engineering (ECE). His research work was supervised by Dr. Suresh Purini. Here’s a summary of Shashwat Shrivastava’s thesis FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation:

Stereo vision is a technique for depth estimation using two input images taken from slightly displaced cameras at the same time. This has many applications in areas such as robotics, driver-less cars, and 3D scene reconstruction. Semi-Global Matching method for stereo vision is quite popular as it is computationally tractable when compared with other global methods and accurate at the same time. In this thesis, we propose a fully parallel and pipelined architecture for Semi-Global Matching with Census Transform being used underneath. Further, we extend the above streaming architecture so that multiple pixels can be processed in a data parallel fashion. We expose this data parallelism through dependency relaxation. This establishes a trade-off between accuracy and throughput of the hardware. We tested the proposed architecture on Virtex-7 FPGA using KITTI 2012 and KITTI 2015 datasets. On images of resolution 1280×960, with 64 disparity levels, we are able to run our hardware design at 100 MHz. At this frequency, our design is able to process 322 frames per second which is 1.6 times faster than the state-of-the-art SGM implementation on FPGA. Our system can be scaled to a higher resolution image.