Dr. Zia Abbas and his students have presented the following papers at the 67th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS-2024), held at Springfield, MA, USA from 11 to 14 August:
- A PVT Compensation Technique for Ring VCO in Charge-Pump PLL – Mehul Saraswat*, Rajesh Mahadev*, Shameer Basha, and Zia Abbas [*Equal authorship]
Here is the summary of the research work as explained by the authors:
Voltage-Controlled Oscillator (VCO) is a crucial component of a Phase-Locked Loop (PLL) system. However, the frequency of a typical Ring-Oscillator-based VCO varies by about 2-3 times across its frequency tuning range and process, voltage and temperature (PVT) conditions. The gain of a Ring-VCO is another crucial parameter that is significantly affected by PVT variations, thereby impacting the stability and loop bandwidth of the PLL. This paper describes a compensation technique to minimize variations in Ring-VCO gain across PVT conditions. A Charge-Pump PLL operating at 4 GHz is implemented in a 28nm CMOS process. The gain of the Ring-VCO varies by ±27% across PVT at 4 GHz. This gain variation of Ring-VCO combined with other PVT-dependent blocks of PLL lead to a deviation of ±60% in Loop Bandwidth and ±21% in Phase-Margin (PM). Process trimming reduces the VCO gain variation to ±25%. Subsequently, the temperature compensation technique reduces the VCO gain variation by 3 times to ±8%, over a temperature range -40°C to 125°C. The resulting variations in Loop Bandwidth and PhaseMargin are reduced to ±34%, and ±15%, respectively.
- A 0.6V, 13nW, 0.0012%/V Line Sensitivity PVT-Invariant Voltage Reference without using Resistors and Amplifiers – Chetan Mittal; Ramgopal Jalluri; K M Le, Analog Intelligent Design, Inc., CA, USA and Zia Abbas
Here is the summary of the research work as explained by the authors:
This paper presents a low-voltage, low-power PVTinvariant voltage reference with excellent line sensitivity for IoT and biomedical applications. By applying a bias current(Ibias) in an NMOS-based composite pair and bias voltage(Vbias) at the body of NMOS to get the temperature-compensated voltage reference over a wide temperature range. The proposed design implemented in a 180nm CMOS process gives an output of 141mV which is independent of process, voltage, and temperature. Without trimming, the process variation of the proposed design is 0.988%(σ/µ), and the temperature coefficient of the proposed voltage reference is 23ppm/oC over a wide temperature range of -40oC to 100oC. For a supply voltage ranging from 0.6V – 2.1V the line sensitivity of the reference is 0.0012%/V. The simulated results show that the proposed voltage reference could operate on a minimum supply of 0.6V, and the power supply rejection ratio at 1-Hz is -85dB. The area occupied by the total circuit is 0.0085mm2 , while the total power consumption of the design is 13nW at the typical corner of 27oC and 0.6V supply.
- A Trim-free PVT Invariant Current Reference with 0.48% process inaccuracy using Vth Tracking Approach – Kuncham Vishnu*, Pradhith Vulichi*, Aniketh Atmakuri*, Ramgopal Jalluri*, Chetan Mittal, and Zia Abbas [*Equal authorship]
Here is the summary of the research work as explained by the authors:
The prevalence of MOSFETs in diverse electronic applications highlights their significance. However, the sensitivity of MOSFET threshold voltage to process variation poses a substantial challenge in achieving consistent device performance. This paper proposes a novel approach to overcome this challenge by employing a threshold voltage (VTH) tracking circuit that tracks the variation in VTH. Our primary objective is to develop a current reference that remains invariant across process, voltage, and temperature (PVT) variations, eliminating the need for an external trimming circuit. This is achieved by the meticulous integration of VTH tracking circuit, CTAT generator, PTAT generator, and a current adder. By employing this design, a process variation ( σ µ ) of 0.48%, a temperature coefficient (TC) of 210ppm/ ◦C for a temperature range of −40◦C to 120◦C, and a line sensitivity of 1.6% is achieved over a voltage range of 1.6V − 3V. The proposed circuit occupies an area of 0.013mm2 while consuming power of 56µW at a typical corner of 27◦C and a supply of 1.8V. The given circuit is implemented in a 180nm CMOS process node with a generated reference current of 61nA.
- Design and Optimization of Robust Process Monitors – Shiva Sharma*, Koushik De*, Sahishanvi Bhartipudi, and Zia Abbas [*Equal authorship]
Here is the summary of the research work as explained by the authors:
This paper presents a new approach to efficient process monitor (PMON) design. It focuses on robust process tracking of PMOS and NMOS devices while minimizing the effects of external factors such as die temperature variations and local supply voltage changes. The proposed design method introduces a comprehensive set of PMON libraries tailored for the specific device types provided by a target technology node. Central to this method is a novel design automation routine based on Zero Temperature Coefficient (ZTC) biasing of a ring oscillator-based PMON. This work demonstrates the effectiveness and scalability of the proposed method across multiple process nodes. The generated PMON structures show a multi-fold improvement in sensitivity for process tracking compared to current state-of-the-art solutions.
Conference homepage: https://www.mwscas2024.org/
August 2024