December 2022

Gourishetty Shirisha received her Master of Science – Dual Degree in  Electronics and Communication Engineering (ECE).  Her research work was supervised by Dr. Zia Abbas. Here’s a summary of her research work on The variations aware Algorithm driven optimisation and performance Modeling approach for CMOS/FinFET Circuits:

Semiconductor Industry has undergone rapid miniaturization in recent decades due to advances in manufacturing technology and the demand for more functionality per chip area. However, scaling down metal-oxide-semiconductor field-effect transistors (MOSFETs) offer many advantages in terms of functionality and speed; it also poses many challenges like increased leakage power. A shrink in device size leads to lowering the threshold voltage to meet the functionality metrics. Due to the inverse relationship of leakage power with the threshold voltage, a rapid increase in leakage power is encountered. In deep sub-micron technologies, static power is dominant over dynamic power, leading to an urgent need for leakage reduction techniques. The primary outcome of scaling down transistors is a reduction in propagation delay. This is achieved by the lowering of threshold voltage and oxide thickness. However, as this comes with the higher cost of increased sub-threshold leakage current, scaling down of Vt is restricted. Hence, the need for delay optimization techniques. 

Another major issue associated with the miniaturization of MOSFETs is the variation of process parameters. Due to scaled-down devices, slight variation in process parameters impacts significantly on performance and yield of the devices. In addition, external environmental changes like temperature and supply voltage variations also affect the performance parameters like delay and leakage by affecting device densities and switching activities of various blocks. Hence, Process variations, Voltage and Temperature (PVT) are the key factors to be considered while optimizing a circuit. Furthermore, aging due to Negative-bias temperature instability (NBTI) affects the delay of the circuit. So, NBTI aging should be considered in delay optimization, for manufacturing more reliable and long-life devices. 

The above factors call for the indispensable need for leakage-delay optimization techniques. Hence, in this research, we propose a multi-objective algorithm-based leakage-delay optimization approach. We used various intuitive multi-objective algorithms to model device parameters such as the Width (W) and Length (L) of a MOSFET. Considering PVT variations for low-power optimization and Process, Supply Voltage, Temperature and Aging (PVTA) variations for high-performance applications, we have applied various swarm-based and genetic algorithms on basic and complex benchmark circuits and obtained up to 70% optimization of Leakage power with PVT and 30% optimization of propagation delays with PVTA conditions. Further, we developed an automated framework of algorithms to analyze the characteristics of a given circuit, choose the appropriate algorithm and load-based sizing to replace in a given circuit for obtaining the required performance metrics. In addition, we have proposed Backward traversal replacement and Partitioning large cells methods for enhanced optimisation of complex cells. 

The next step to further optimize this optimization process of the circuits is to eliminate the inherent extensive run time taken by the SPICE tool. The algorithm optimization process involves the calculation of circuit performances like leakage and propagation delay for huge samples. Moreover, with the scaled down technology nodes, statistical variation aware analysis has gained importance, which also involves large number of circuit performance calculations. SPICE tool is widely used to calculate the circuit performances and computing results of an extensive sample set with the SPICE tool is time complex. Hence, we proposed a statistical variation aware estimation models based on machine learning techniques like Polynomial Regression and Artificial Neural Networks (ANN), which replaces the SPICE tool with <1% Error and 10,000 times reduction in time complexity.