Battu Balaji Yadav received his MS in Electronics and Communication Engineering (ECE). His research work was supervised by Dr. Zia Abbas. Here’s a summary of Battu Balaji Yadav’s MS thesis, Low Quiescent Current,Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance as explained by him:
The enormous proliferation of battery-operated portable devices such as cell phones, laptops, wireless sensor networks, etc. has made power management one of the major concerns in IC industry. The power management is being allocated an ever-higher priority by trying to sustain the life of the batteries and hence the whole device powered by this battery. In this scenario, low-dropout (LDO) voltage regulators have turned into the desired choice for low-voltage on-chip power management solutions because of their fast response, low power, and low cost of implementation. Designing an Output Capacitorless LDO achieving better load/line regulation and transient characteristics with low quiescent current consumption has been a major challenge for analog designers.
This thesis presents a novel low-power, area-efficient and output capacitor-less LDO that satisfies all primary requirements of power mapping for a Power Management IC (PMIC). The design introduces a dynamically biased feedback resistor which responds instantly to the output voltage variations, thereby achieving better load transient behaviour. Besides, the employed adaptive-biasing technique contributes to architectural transformation to attain stability over a wider range of load currents (0-100mA). It provides a regulated voltage of 1.87V from a supply ranging from 1.92V to 3.6V with a reported load and line regulation of 0.00136mV/mA and 0.078mV/V respectively. Moreover, the circuit potentially supports the load transients either from 0A to 100mA or 100mA to 0A with a rise and fall times of 10μs. The achieved overshoot and undershoot values are 160mV and 154mV respectively. Hence, it demonstrates a substantial steady-state and transient performance with low-power thus making it suitable to be used in PMIC for battery-operated portable devices.
This work also focused in designing a PVT invariant current reference whose stability decides the stable operating point of the Error Amplifier (EA) used in LDO design. The designed current reference has achieved a low figure-of-merit (FOM) of 1.3501ppm/OC2on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed, and a β-multiplier is used to compensate for mobility (μ)and threshold voltage (Vth). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/OC over a wide temperature range of -50OC to100OC is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed.
In addition, a CMOS-only ultra-low power voltage reference of 0.925V is designed to provide stable to reference to the proposed LDO so that to attain stable regulated output voltage. it achieved a temperature coefficient (TC) of 3.75ppm/OC over a wide temperature range of -55OC to 140OC with 27nW power consumption.