Ayan Biswas supervised by Dr. Anoop M. Namboodiri received his Master of Science – Dual Degree in Computer Science & Engineering (LCD). Here’s a summary of his research work on Characterizing Face Recognition for Resource Efficient Deployment on Edge

Deployment of Face Recognition (FR) systems on edge devices has seen significant growth, driven by advances in hardware and neural architectures. However, tailoring State-of-the-art (SOTA) FR solutions to specific edge environments remains difficult and largely unexplored. Although benchmark data exists for some combinations of model, hardware, and frameworks, it does not scale to the evaluation of custom or modified architectures. Furthermore, theoretical metrics such as Floating-Point Operations (FLOPs) are often poor predictors of real-world performance, as edge inference throughput is frequently constrained by system-level factors including data movement, memory access, and pipeline overheads. This limitation arises from a combinatorial design space spanning architectural variants, input resolutions, deployment frameworks, and hardware configurations, making exhaustive benchmarking infeasible. An analysis of recent FR literature performed in this thesis reveals that while substantial innovation is concentrated in loss functions, training strategies, and data augmentation, the underlying Convolutional Neural Network (CNN) backbone is routinely treated as a fixed abstraction. These backbones are typically inherited from large-scale image classification, where models are optimized to separate visually distinct categories, whereas FR requires learning discriminative embeddings that distinguish between highly similar identities. Consequently, the exploration of lightweight, task-specific architectures for edge deployment remains limited. To address this gap, this thesis models the relationship between network architecture and inference throughput in an edge deployment setting, demonstrating that throughput follows a predictable structure when grouped by architectural families. Building on this modeling, this work proposes a data-efficient, architecture-aware framework to estimate the throughput of custom FR models from a sparse set of empirical measurements, with predictions that are explainable and exhibit errors small enough to be treated as standard on-device observational noise. Further, Face Anti-Spoofing (FAS) pipelines are evaluated to quantify the trade-offs between inference throughput and error rates, highlighting deployment challenges arising from specialized operations that do not map efficiently to standard edge-acceleration frameworks. In parallel, empirical experimentation on FR backbones is conducted to characterize the trade-off between discriminative power and inference throughput, and its impact on deployability on edge hardware, revealing non-linear scaling behavior and throughput saturation driven by data pipeline constraints. Collectively, these findings address a key gap in FR deployment: the absence of a scalable mapping between architectural design and on-device inference performance for custom models. By establishing an explainable mapping from model architecture to throughput, the proposed framework enables systematic performance estimation without exhaustive benchmarking, supporting hardware-aware design and exploration of custom architecture for FR. To the best of the author’s knowledge, this is the first work to directly address this problem. The complete benchmarking suite and source code are publicly available at https://github.com/AyanBiswas19/Resource_Efficient_FR.

July 2026