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Accelerator Design Hackathon – 2018

The Accelerator Design Hackathon – 2018 was conducted in IIIT-H from 30 April – 4 May. The workshop was open to all full-time students from any recognized educational institute in India.  The aim of this hackathon was to enable students to do an accelerator design, to solve any problem in the student’s domain of interest. Hackathon-2018 was supported by BlueSpec and Microsoft. There were 27 teams who had registered for the hackathon but only 22 teams completed the registration for the Catapult cluster account and were assigned a catapult node.

The five day hackathon included the following aspects:

  • Keynote by Dr. Chidamber Kulkarni, CTO of rENIAC on Why and What of Accelerators and FPGAs?
  • Bluespec System Verilog Introduction by Mr. Niraj Sharma, Head India BlueSpec
  • Basic syntax and Semantics of Bluespec by Mr. Niraj Sharma
  • Hands-on-exercises, Bubble sort in Bluespec
  •  Interfaces and Transaction level modeling in Bluespec by Mr. Niraj Sharma
  • Getting started with Catapult User Guide, Lavanya
  •  Interfacing Bluespec verilog code with the SimpleRole.sv, Implement and generate FPGA bit file. verifying it using the visual studio cpp testcase
  • Identify a design problem and implement it in Bluespec and FPGA of the Catapult node and verify the same on the catapult node
  • Mentoring of the students by Suresh and Lavanya

Accelerator Design Hackathon – 2018 gave a great variety of experience to the students.  There was a variety in the projects attempted by the students, ranging from finding dot-product of vectors to CNN accelerators. Some students could successfully implement Convolutional Neural Networks and Viola-Jones Face detection on the Catapult cluster, while some teams needed lot of hand-holding and support and could not complete the implementation in 3 days as they were completely new to Bluespec and Catapult.