Meet The Ritesh Tiwari Outstanding MS Thesis Award Winner 2026

Mohammad Rehan Akhtar has won the award for his Master’s thesis that integrates three traditionally separate domains of integrated circuit design: device-level physics, machine learning-based modeling, and circuit-level characterization. The award was conferred on him at the annual convocation held on 11 July 2026.

For most of us, gadgets such as smartphones, laptops, home appliances, features in cars that we drive, healthcare equipment, traffic lights, ATMs, and more are just everyday devices that are ubiquitous, and we rarely stop to think about the tiny chips inside that make their functioning possible. For Mohammad Rehan Akhtar, however, those chips became the centre of a research journey that combined electronics, machine learning, and persistence to tackle some of the semiconductor industry’s most pressing challenges.

Outstanding MS Thesis
His thesis, Integrated Standard Cell Characterization and Complex Circuit Analysis in CMOS/FinFET Digital Circuit Design, won him the Ritesh Tiwari Masters Thesis Award for the year 2026. It is an annual endowment award given to recognize and honor the most outstanding Master of Science (MS) thesis defended at IIIT-H during the academic year. The award was established by Smt. Vijay Kumari Sharma in memory of her son, Ritesh Kumar Tiwari. Ritesh was an MS student at IIIT-H working under Prof. Kamal Karlapalem, whose promising research in attack-resilient protocols, access control, and semantic web security was cut short when he passed away from leukemia in 2009. Rehan’s award-winning research which was undertaken under the supervision of Prof. Zia Abbas, has focused on improving the way chips are designed, making them faster, more power-efficient, and more reliable over time. The work has already led to multiple research publications and industry recognition.  

Selection Process
There is a detailed recommendation process for the award, the format for which has been designed by Prof. Karlapalem. “Faculty can nominate their students based on certain criteria such as novelty of the problem addressed, the exact contribution made by the student, impact other than publications and so on,” explains Prof. Praveen Paruchuri, who is part of a committee that goes on to individually evaluate each nomination received.The same details are then shared with the committee along with a weighing scheme for each criteria. “The committee members would then share their score for each candidate. Once collated, if there is a consistently high rated thesis, that emerges as the winner,” he says. 

Research Explained
Designing modern semiconductor chips is an enormously complex process. Engineers constantly balance competing objectives: chips must perform tasks quickly, consume as little power as possible, and continue functioning reliably for years. Rehan’s research centred on these three critical metrics. Delay refers to how quickly a chip responds to an input. The smaller the delay, the faster the performance. Then there’s power consumption, which affects battery life and energy efficiency- especially important in mobile devices. Finally, there is aging, a less visible but equally important challenge. Traditionally, evaluating these factors requires extensive simulations that are both computationally expensive and dependent on specialised software tools. Rehan wondered whether machine learning could help.

Teaching Machines to Predict Chip Performance
At the heart of Rehan’s thesis is a simple idea: instead of running costly simulations repeatedly, train machine learning models to predict how a chip will perform. Using datasets generated from chip designs, Rehan developed machine learning frameworks capable of estimating performance characteristics at much larger scales. This approach dramatically speeds up the design process while reducing reliance on expensive simulation environments. “Not only is it it faster compared to what we generally do, it can be shifted to a less license-dependent approach,” explains Rehan. 

But building accurate machine learning systems for chip design is not straightforward. Designers must navigate enormous design spaces involving dozens of interdependent parameters. To address this challenge, Rehan integrated advanced optimisation techniques, including genetic algorithms and multi-objective optimisation methods, allowing the models to identify better design choices more efficiently.

Reducing Error, Improving Accuracy 
One of the key achievements of the research was improving prediction accuracy. Earlier approaches often produced error rates of around 10 percent when estimating chip characteristics. Rehan’s architecture significantly improved those results. “We were able to achieve approximately 2 to 3 percent errors as compared to the 10 % that we achieved earlier.” The improvement was particularly notable because it was achieved using smaller datasets and faster simulations, making the solution both practical and scalable.

A First for FinFET Technology
Perhaps the most significant outcome of the thesis was research focused on FinFET technology, one of the dominant transistor architectures used in today’s semiconductor industry. While previous work had largely concentrated on older CMOS technologies, Rehan’s research addressed reliability and aging issues in FinFET devices using machine learning-driven optimisation. “We were able to mitigate the aging factor in FinFET using device sizing methodology,” remarks Rehan, referring to the fin-shaped 3D non-planar transistor. The novelty of the work contributed to the acceptance of a paper in the IEEE Transactions on Computer-Aided Design of Circuits and Systems journal. At the modeling level, the research introduces PIDArc, a novel physics-informed machine learning architecture designed to capture complex leakage power behavior under aging and variation conditions. This led to a paper that has been published by IEEE at the prestigious 2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID). At the circuit level, the OptiMo framework extends the analysis to complex digital circuits by enabling automated estimation and optimization of delay and leakage power.

Research by Discovery
Interestingly, Rehan did not enter IIITH with a clear plan to become a researcher. After completing his BTech in West Bengal, he joined the institute through the Postgraduate Entrance Examination (PGEE) in 2022. His initial interest lay broadly in chip design and data-driven applications rather than machine learning itself. “I was not aware of the machine learning part because I’m from the ECE background,” he says. That however changed once he arrived on campus.

As he explored the intersection of data science and semiconductor design, he began identifying industry challenges that could benefit from machine learning solutions. His search for a faculty advisor eventually led him to Prof. Zia Abbas. “My core interest is in chip design. When I discovered that a lot of Prof. Zia’s work is based on machine learning, it piqued me enough to work with him.” 

Like most research journeys, Rehan’s was far from linear. “The journey was full of ups and downs,” he admits. There were rejected papers, revised experiments, and repeated iterations. Those setbacks ultimately strengthened the work, not only proving the student-advisor partnership fruitful but also resulting in multiple publications and a strong research portfolio. 

Today, Rehan works in Qualcomm contributing to the design and verification of large-scale semi-conductor systems. “I’m currently occupied with the timing analysis of bigger chips, like the Snapdragon chips which go into mobiles and servers,” he says. While Rehan may have miles to go, his journey so far has already produced research that could help shape the future of semiconductor design.